In a microprocessor or other electronics device within a computer system, various logic circuits, such as processing cores, may request data from other logic circuits within or outside of the microprocessor or computer system, which may be stored, at least temporarily, within the requesting logic circuit's cache memory for the logic circuit to use. Accordingly, requesting logic circuits and other electronic devices may be referred to as “cache agents”.
Cache agents may communicate with other cache agents or semiconductor devices within a computer system by transmitting messages across an interconnect, such as a point-to-point (P2P) network. Messages may include a data portion and an address portion, which identifies a target recipient of the data portion. Furthermore, the data portion and address portion of the messages may be sent by cache agents along different communication paths, or “channels”. For example, within a multi-core processor (a processor having more than one logic to process instructions), cache agents may transmit data and corresponding address information within the multi-core processor along separate communication paths before the address and data combine into a single message to be transmitted to a target recipient located inside or outside of the multi-core processor.
Because data and addresses transmitted by a cache agent may traverse communication paths of different lengths and delay characteristics, there may be no guarantee that the proper address will be transmitted within a single message with the proper data to which the address corresponds. Furthermore, the problem is exacerbated as more cache agents transmit data and address information along the same two communication paths before being combined and transmitted to a target recipient.
FIG. 1, for example, illustrates an arrangement of cache agents in which the data transmitted by each cache agent traverses a data network communication path and in which the addresses transmitted by each cache agent traverse an address network communication path before being combined into a single message to be transmitted to a target recipient. The cache agents of FIG. 1 may be within a multi-core processor, for example, and the merge block may be an interface to a network of devices within a computer system interconnected by a shared bus or point-to-point interconnect.
If the proper data and corresponding addresses are not properly combined when transmitted in a message to a target recipient, the wrong target recipient may receive the data, which can result in system errors.